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HPCA
2009
IEEE
14 years 9 months ago
In-Network Snoop Ordering (INSO): Snoopy coherence on unordered interconnects
Realizing scalable cache coherence in the many-core era comes with a whole new set of constraints and opportunities. It is widely believed that multi-hop, unordered on-chip networ...
Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha
CHI
2007
ACM
14 years 9 months ago
Work-centered design: a case study of a mixed-initiative scheduler
We present the case study of a complex, mixed-initiative scheduling system to illustrate Work-Centered Design (WCD), a new approach for the design of information systems. WCD is b...
Keith A. Butler, Jiajie Zhang, Chris Esposito, Ali...
HPCA
2008
IEEE
14 years 9 months ago
Regional congestion awareness for load balance in networks-on-chip
Interconnection networks-on-chip (NOCs) are rapidly replacing other forms of interconnect in chip multiprocessors and system-on-chip designs. Existing interconnection networks use...
Paul Gratz, Boris Grot, Stephen W. Keckler
HPCA
2007
IEEE
14 years 9 months ago
HARD: Hardware-Assisted Lockset-based Race Detection
The emergence of multicore architectures will lead to an increase in the use of multithreaded applications that are prone to synchronization bugs, such as data races. Software sol...
Pin Zhou, Radu Teodorescu, Yuanyuan Zhou
HPCA
2006
IEEE
14 years 9 months ago
Efficient instruction schedulers for SMT processors
We propose dynamic scheduler designs to improve the scheduler scalability and reduce its complexity in the SMT processors. Our first design is an adaptation of the recently propos...
Joseph J. Sharkey, Dmitry V. Ponomarev