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ESTIMEDIA
2006
Springer
13 years 11 months ago
Use of a Bit-true Data Flow Analysis for Processor-Specific Source Code Optimization
Nowadays, key characteristics of a processor's instruction set are only exploited in high-level languages by using inline assembly or compiler intrinsics. Inserting intrinsic...
Heiko Falk, Jens Wagner, André Schaefer
DSD
2005
IEEE
116views Hardware» more  DSD 2005»
14 years 1 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
DAC
2004
ACM
14 years 8 months ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
EUROSYS
2007
ACM
14 years 4 months ago
Competitive prefetching for concurrent sequential I/O
During concurrent I/O workloads, sequential access to one I/O stream can be interrupted by accesses to other streams in the system. Frequent switching between multiple sequential ...
Chuanpeng Li, Kai Shen, Athanasios E. Papathanasio...
CODES
2005
IEEE
14 years 1 months ago
Conflict analysis in multiprocess synthesis for optimized system integration
This paper presents a novel approach for multiprocess synthesis supporting well-tailored module integration at system level. The goal is to extend the local scope of existing arch...
Oliver Bringmann, Wolfgang Rosenstiel, Axel Sieben...