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» Concurrent Fault Detection in Random Combinational Logic
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ITC
2003
IEEE
141views Hardware» more  ITC 2003»
13 years 12 months ago
Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits
In this paper, a new paradigm for designing logic circuits with concurrent error detection (CED) is described. The key idea is to exploit the asymmetric soft error susceptibility ...
Kartik Mohanram, Nur A. Touba
VMCAI
2009
Springer
14 years 1 months ago
Towards Automatic Stability Analysis for Rely-Guarantee Proofs
The Rely-Guarantee approach is a well-known compositional method for proving Hoare logic properties of concurrent programs. In this approach, predicates in the proof must be proved...
Hasan Amjad, Richard Bornat
DFT
2002
IEEE
121views VLSI» more  DFT 2002»
13 years 11 months ago
Testing Digital Circuits with Constraints
Many digital circuits have constraints on the logic values a set of signal lines can have. In this paper, we present two new techniques for detecting the illegal combinations of l...
Ahmad A. Al-Yamani, Subhasish Mitra, Edward J. McC...
ISSTA
2012
ACM
11 years 9 months ago
Swarm testing
Swarm testing is a novel and inexpensive way to improve the diversity of test cases generated during random testing. Increased diversity leads to improved coverage and fault detec...
Alex Groce, Chaoqiang Zhang, Eric Eide, Yang Chen,...
SCP
1998
138views more  SCP 1998»
13 years 6 months ago
A Hierarchy of Constraint Systems for Data-Flow Analysis of Constraint Logic-Based Languages
Many interesting analyses for constraint logic-based languages are aimed at the detection of monotonic properties, that is to say, properties that are preserved as the computation...
Roberto Bagnara