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» Concurrent Methodologies for Global Optimization
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ICCAD
2002
IEEE
154views Hardware» more  ICCAD 2002»
14 years 5 months ago
Concurrent flip-flop and repeater insertion for high performance integrated circuits
For many years, CMOS process scaling has allowed a steady increase in the operating frequency and integration density of integrated circuits. Only recently, however, have we reach...
Pasquale Cocchini
IJON
2007
102views more  IJON 2007»
13 years 8 months ago
Methodology for long-term prediction of time series
In this paper, a global methodology for the long-term prediction of time series is proposed. This methodology combines direct prediction strategy and sophisticated input selection...
Antti Sorjamaa, Jin Hao, Nima Reyhani, Yongnan Ji,...
ICCAD
1997
IEEE
90views Hardware» more  ICCAD 1997»
14 years 27 days ago
A hierarchical decomposition methodology for multistage clock circuits
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
Gary Ellis, Lawrence T. Pileggi, Rob A. Rutenbar
ISPD
1999
ACM
97views Hardware» more  ISPD 1999»
14 years 1 months ago
A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design
This paper presents a methodology to analyze signal integrity such as power voltage drop and clock skew in early stages of design, more specifically, when RTL-design and early flo...
Masato Iwabuchi, Noboru Sakamoto, Yasushi Sekine, ...
ICASSP
2011
IEEE
13 years 12 days ago
A methodology based on Transportation problem modeling for designing parallel interleaver architectures
For high-data-rate applications, turbo-like iterative decoders are implemented with parallel hardware architecture. However, to achieve high throughput, concurrent accesses to each...
Awais Sani, Philippe Coussy, Cyrille Chavet, Eric ...