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4299
search results - page 28 / 860
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Concurrent Test Generation
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VTS
1996
IEEE
75
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Hardware
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VTS 1996
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A new test pattern generation method for delay fault testing
14 years 18 days ago
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www.lirmm.fr
S. Cremoux, Christophe Fagot, Patrick Girard, Chri...
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23
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DAC
1992
ACM
93
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Computer Architecture
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DAC 1992
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SWiTEST: A Switch Level Test Generation System for CMOS Combinational Circuits
14 years 16 days ago
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poisson.usc.edu
Kuen-Jong Lee, Charles Njinda, Melvin A. Breuer
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8
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STVR
2008
53
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STVR 2008
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IPOG/IPOG-D: efficient test generation for multi-way combinatorial testing
13 years 8 months ago
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csrc.nist.gov
Yu Lei, Raghu Kacker, D. Richard Kuhn, Vadim Okun,...
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22
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JISE
2000
71
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JISE 2000
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Compact Test Generation Using a Frozen Clock Testing Strategy
13 years 8 months ago
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www.iis.sinica.edu.tw
Elizabeth M. Rudnick, Miron Abramovici
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32
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TAP
2009
Springer
178
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Hardware
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TAP 2009
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Dynamic Symbolic Execution for Testing Distributed Objects
14 years 3 months ago
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heim.ifi.uio.no
Abstract. This paper extends dynamic symbolic execution to distributed and concurrent systems. Dynamic symbolic execution can be used in software testing to systematically identify...
Andreas Griesmayer, Bernhard K. Aichernig, Einar B...
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