This paper presents an efficient approach to generate tests for gate delay faults. Unlike other known algorithms which try to generate a 'good' delay test the presented ...
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaud...
To assist in dynamic assertion-based verification, we present a method to automatically build a test vector generator from a temporal property. Based on the duality between monito...
Generating test data for formal state based specifications is computationally expensive. This paper improves a framework that addresses this issue by representing the test data ge...
Karnig Derderian, Mercedes G. Merayo, Robert M. Hi...
Under certain constraints the test case generation problem can be represented as a model checking problem, thus enabling the use of powerful model checking tools to perform the te...