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GLVLSI
1996
IEEE
125views VLSI» more  GLVLSI 1996»
14 years 1 months ago
Performance-Driven Interconnect Global Routing
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
Dongsheng Wang, Ernest S. Kuh
ICCAD
1996
IEEE
122views Hardware» more  ICCAD 1996»
14 years 1 months ago
Analytical delay models for VLSI interconnects under ramp input
Elmore delay has been widely used as an analytical estimate of interconnect delays in the performance-driven synthesis and layout of VLSI routing topologies. However,for typical R...
Andrew B. Kahng, Kei Masuko, Sudhakar Muddu
ISLPED
1996
ACM
100views Hardware» more  ISLPED 1996»
14 years 1 months ago
Basic experimentation on accuracy of power estimation for CMOS VLSI circuits
In this paper, we discuss on accuracy of several kinds of power dissipation model for CMOS VLSI circuits. Some researchers have proposed several efficient power estimation methods...
Tohru Ishihara, Hiroto Yasuura
ASIACRYPT
2007
Springer
14 years 26 days ago
On Efficient Message Authentication Via Block Cipher Design Techniques
In an effort to design a MAC scheme that is built using block cipher components and runs faster than the modes of operation for message authentication, Daemen and Rijmen have propo...
Goce Jakimoski, K. P. Subbalakshmi
EVOW
2009
Springer
14 years 23 days ago
A Hierarchical Classification Ant Colony Algorithm for Predicting Gene Ontology Terms
Abstract. This paper proposes a novel Ant Colony Optimisation algorithm for the hierarchical problem of predicting protein functions using the Gene Ontology (GO). The GO structure ...
Fernando E. B. Otero, Alex Alves Freitas, Colin G....