A methodology for supporting dynamic voltage scaling (DVS) on commercial FPGAs is described. A logic delay measurement circuit (LDMC) is used to determine the speed of an inverter...
C. T. Chow, L. S. M. Tsui, Philip Heng Wai Leong, ...
We investigate defects in CMOS domino gates and derive the test conditions for them. Very-Low-Voltage Testing can improve the defect coverage, which we define as the maximum detec...
Simulation with Arena is used to analyze a controlled conveyor network with merging configuration (CNMC). We use simulation to realize the logic in a queueingtheoretic model (QTM)...
To incorporate instant effects and different timescales within a single biological system, an extension of discrete regulatory networks with short-term stimuli is proposed. By mai...
The strategy for natural language interpretation presented in this paper implements the dynamics of context change by translating natural language texts into a meaning representat...