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DATE
2004
IEEE
146views Hardware» more  DATE 2004»
14 years 15 days ago
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies
In multimedia and other streaming applications a significant portion of energy is spent on data transfers. Exploiting data reuse opportunities in the application, we can reduce th...
Ilya Issenin, Erik Brockmeyer, Miguel Miranda, Nik...
ICCD
2005
IEEE
246views Hardware» more  ICCD 2005»
14 years 5 months ago
H-SIMD Machine: Configurable Parallel Computing for Matrix Multiplication
FPGAs (Field-Programmable Gate Arrays) are often used as coprocessors to boost the performance of dataintensive applications [1, 2]. However, mapping algorithms onto multimillion-...
Xizhen Xu, Sotirios G. Ziavras
CSREAESA
2009
13 years 9 months ago
Built-In Self-Test of Embedded SEU Detection Cores in Virtex-4 and Virtex-5 FPGAs
A Built-In Self-Test (BIST) approach is presented for the Internal Configuration Access Port (ICAP) and Frame Error Correcting Code (ECC) logic cores embedded in Xilinx Virtex-4 an...
Bradley F. Dutton, Charles E. Stroud
DATE
2008
IEEE
133views Hardware» more  DATE 2008»
14 years 3 months ago
Memory Organization with Multi-Pattern Parallel Accesses
We propose an interleaved memory organization supporting multi-pattern parallel accesses in twodimensional (2D) addressing space. Our proposal targets computing systems with high ...
Arseni Vitkovski, Georgi Kuzmanov, Georgi Gaydadji...
FCCM
1998
IEEE
111views VLSI» more  FCCM 1998»
14 years 1 months ago
A Stream-Based Configurable Computing Radio Testbed
Software radios have emerged as important tools in the development of new signal processing algorithms, networking protocols, and propagation experiments in wireless environments....
Steven Swanchara, Scott J. Harper, Peter M. Athana...