Sciweavers

734 search results - page 90 / 147
» Configurable Transactional Memory
Sort
View
ASPLOS
2008
ACM
13 years 10 months ago
Concurrency control with data coloring
Concurrency control is one of the main sources of error and complexity in shared memory parallel programming. While there are several techniques to handle concurrency control such...
Luis Ceze, Christoph von Praun, Calin Cascaval, Pa...
ICCSA
2010
Springer
13 years 10 months ago
An Identifiable Yet Unlinkable Authentication System with Smart Cards for Multiple Services
The purpose of this paper is to realize an authentication system which satisfies four requirements for security, privacy protection, and usability, that is, impersonation resistanc...
Toru Nakamura, Shunsuke Inenaga, Daisuke Ikeda, Ke...
VLSID
2008
IEEE
138views VLSI» more  VLSID 2008»
14 years 9 months ago
Memory Architecture Exploration Framework for Cache Based Embedded SOC
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindaraj...
HPCA
2007
IEEE
14 years 9 months ago
Fully-Buffered DIMM Memory Architectures: Understanding Mechanisms, Overheads and Scaling
Performance gains in memory have traditionally been obtained by increasing memory bus widths and speeds. The diminishing returns of such techniques have led to the proposal of an ...
Brinda Ganesh, Aamer Jaleel, David Wang, Bruce L. ...
CODES
2006
IEEE
14 years 2 months ago
Data reuse driven energy-aware MPSoC co-synthesis of memory and communication architecture for streaming applications
The memory subsystem of a complex multiprocessor systemson-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as...
Ilya Issenin, Nikil Dutt