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» Considering an Organization's Memory
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SAC
2006
ACM
14 years 3 months ago
Building the functional performance model of a processor
In this paper, we present an efficient procedure for building a piecewise linear function approximation of the speed function of a processor with hierarchical memory structure. Th...
Alexey L. Lastovetsky, Ravi Reddy, Robert Higgins
CC
2003
Springer
14 years 2 months ago
Improving Data Locality by Chunking
Cache memories were invented to decouple fast processors from slow memories. However, this decoupling is only partial, and many researchers have attempted to improve cache use by p...
Cédric Bastoul, Paul Feautrier
ISCA
2000
IEEE
63views Hardware» more  ISCA 2000»
14 years 1 months ago
An embedded DRAM architecture for large-scale spatial-lattice computations
Spatial-lattice computations with finite-range interactions are an important class of easily parallelized computations. This class includes many simple and direct algorithms for ...
Norman Margolus
ARVLSI
1997
IEEE
105views VLSI» more  ARVLSI 1997»
14 years 1 months ago
An Embedded DRAM for CMOS ASICs
The growing gap between on-chip gates and off-chip I/O bandwidth argues for ever larger amounts of on-chip memory. Emerging portable consumer technology, such as digital cameras, ...
John Poulton
DAC
2010
ACM
13 years 7 months ago
Xetal-Pro: an ultra-low energy and high throughput SIMD processor
This paper presents Xetal-Pro SIMD processor, which is based on Xetal-II, one of the most computational-efficient (in terms of GOPS/Watt) processors available today. XetalPro supp...
Yifan He, Yu Pu, Richard P. Kleihorst, Zhenyu Ye, ...