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DFT
2005
IEEE
132views VLSI» more  DFT 2005»
14 years 24 days ago
Low Power BIST Based on Scan Partitioning
A built-in self-test (BIST) scheme is presented which both reduces overhead for detecting random-pattern-resistant (r.p.r.) faults as well as reduces power consumption during test...
Jinkyu Lee, Nur A. Touba
IPPS
2003
IEEE
14 years 4 months ago
Loop Dissevering: A Technique for Temporally Partitioning Loops in Dynamically Reconfigurable Computing Platforms
This paper presents a technique, called loop dissevering, to temporally partitioning any type of loop presented in programming languages. The technique can be used in the presence...
João M. P. Cardoso
ISLPED
2003
ACM
82views Hardware» more  ISLPED 2003»
14 years 4 months ago
Multivoltage scheduling with voltage-partitioned variable storage
Multivoltage scheduling (MVS) for datapaths offers the energy savings of voltage scaling on a per-operation basis with a voltage aware operator scheduling. This work investigates...
Amitabh Menon, S. K. Nandy, Mahesh Mehendale
ISSS
1997
IEEE
109views Hardware» more  ISSS 1997»
14 years 3 months ago
Reducing the Complexity of ILP Formulations for Synthesis
Integer Linear Programming ILP is commonly used in high level and system level synthesis. It is an NP-Complete problem in general cases. There exists some tools that give an o...
Anne Mignotte, Olivier Peyran
MICS
2008
124views more  MICS 2008»
13 years 9 months ago
Community Structures of Networks
We present an approach to studying the community structures of networks by using linear programming (LP). Starting with a network in terms of (a) a collection of nodes and (b) a co...
William Y. C. Chen, Andreas W. M. Dress, Winking Q...