743 search results - page 142 / 149 » Constraint Programming Architectures: Review and a New Propo... |
ANLP
1997
13 years 10 months ago
1997
This paper describes a new finite-state shallow parser. It merges constructive and reductionist approaches within a highly modular architecture. Syntactic information is added at ...
HPCA
2008
IEEE
14 years 9 months ago
2008
IEEE
Cache partitioning and sharing is critical to the effective utilization of multicore processors. However, almost all existing studies have been evaluated by simulation that often ...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Several recent processor designs have proposed to enhance performance by increasing the clock frequency to the point where timing faults occur, and by adding error-correcting supp...
NOCS
2010
IEEE
13 years 6 months ago
2010
IEEE
Abstract--The high-performance computing domain is enriching with the inclusion of Networks-on-chip (NoCs) as a key component of many-core (CMPs or MPSoCs) architectures. NoCs face...
NOCS
2010
IEEE
13 years 6 months ago
2010
IEEE
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...