26 search results - page 3 / 6 » Constraint-Based Random Stimuli Generation for Hardware Veri... |
CSCWD
2009
Springer
14 years 1 months ago
2009
Springer
Constrained random simulation methodology still plays an important role in hardware verification due to the limited scalability of formal verification, especially for the large an...
DATE
2008
IEEE
14 years 1 months ago
2008
IEEE
Despite the growing research effort in formal verification, constraint-based random simulation remains an integral part of design validation, especially for large design componen...
VLSID
2002
IEEE
14 years 7 months ago
2002
IEEE
Directed test program-based verification or formal verification methods are usually quite ineffective on large cachecoherent, non-uniform memory access (CC-NUMA) multiprocessors b...
CP
2006
Springer
13 years 11 months ago
2006
Springer
The paper presents a method for generating solutions of a constraint satisfaction problem (CSP) uniformly at random. The main idea is to express the CSP as a factored probability d...
ITC
2003
IEEE
14 years 18 days ago
2003
IEEE
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...