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CODES
2006
IEEE
15 years 10 months ago
System-level power-performance trade-offs in bus matrix communication architecture synthesis
System-on-chip communication architectures have a significant impact on the performance and power consumption of modern multiprocessor system-on-chips (MPSoCs). However, customiza...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,...
VLSID
2002
IEEE
207views VLSI» more  VLSID 2002»
16 years 4 months ago
Synthesis of High Performance Low Power Dynamic CMOS Circuits
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
Debasis Samanta, Nishant Sinha, Ajit Pal
LPNMR
2009
Springer
15 years 11 months ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
ASPDAC
2005
ACM
113views Hardware» more  ASPDAC 2005»
15 years 10 months ago
Scalable interprocedural register allocation for high level synthesis
Abstract— The success of classical high level synthesis has been limited by the complexity of the applications it can handle, typically not large enough to necessitate the depart...
Rami Beidas, Jianwen Zhu
CORR
2010
Springer
162views Education» more  CORR 2010»
15 years 3 months ago
Backward Reachability of Array-based Systems by SMT solving: Termination and Invariant Synthesis
The safety of infinite state systems can be checked by a backward reachability procedure. For certain classes of systems, it is possible to prove the termination of the procedure ...
Silvio Ghilardi, Silvio Ranise