128 search results - page 19 / 26 » Contention-aware application mapping for Network-on-Chip com... |
EUROPAR
2005
Springer
14 years 1 months ago
2005
Springer
Nested-parallelism programming models, where the task graph associated to a computation is series-parallel, present good analysis properties that can be exploited for scheduling, c...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
Lecture Notes
Driven by recent innovations in Field-Programmable Gate Arrays (FPGAs), reconfigurable computing offers unique ways to accelerate key algorithms. FPGAs offer a programmable logic f...
VLSID
2010
IEEE
13 years 11 months ago
2010
IEEE
Network-on-Chip combined with Globally Asynchronous Locally Synchronous paradigm is a promising architecture for easy IP integration and utilization with multiple voltage levels. ...
ISNN
2005
Springer
14 years 1 months ago
2005
Springer
Abstract. Artificial Neural Networks (ANNs) and image processing requires massively parallel computation of simple operator accompanied by heavy memory access. Thus, this type of ...