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DAC
2009
ACM
14 years 9 months ago
Designing heterogeneous ECU networks via compact architecture encoding and hybrid timing analysis
In this paper, a design method for automotive architectures is proposed. The two main technical contributions are (i) a novel hardware/software architecture encoding that unifies ...
Jürgen Teich, Martin Lukasiewycz, Michael Gla...
RTAS
2010
IEEE
13 years 6 months ago
Middleware for Resource-Aware Deployment and Configuration of Fault-Tolerant Real-time Systems
Developing large-scale distributed real-time and embedded (DRE) systems is hard in part due to complex deployment and configuration issues involved in satisfying multiple quality f...
Jaiganesh Balasubramanian, Aniruddha S. Gokhale, A...
ASAP
2000
IEEE
184views Hardware» more  ASAP 2000»
14 years 1 months ago
Tradeoff Analysis and Architecture Design of a Hybrid Hardware/Software Sorter
Sorting long sequences of keys is a problem that occurs in many different applications. For embedded systems, a uniprocessor software solution is often not applicable due to the l...
Marcus Bednara, Oliver Beyer, Jürgen Teich, R...
FPL
2004
Springer
144views Hardware» more  FPL 2004»
14 years 14 days ago
A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms
A recent trend towards integrating FPGAs with many heterogeneous components, such as memory systems, dedicated multipliers, etc., has made them an attractive option for implementin...
Jingzhao Ou, Viktor K. Prasanna
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
14 years 3 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...