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ASYNC
2007
IEEE
154views Hardware» more  ASYNC 2007»
14 years 2 months ago
Design of a High-Speed Asynchronous Turbo Decoder
This paper explores the advantages of high performance asynchronous circuits in a semi-custom standard cell environment for high-throughput turbo coding. Turbo codes are high-perf...
Pankaj Golani, Georgios D. Dimou, Mallika Prakash,...
JCC
2007
121views more  JCC 2007»
13 years 7 months ago
Speeding up parallel GROMACS on high-latency networks
: We investigate the parallel scaling of the GROMACS molecular dynamics code on Ethernet Beowulf clusters and what prerequisites are necessary for decent scaling even on such clust...
Carsten Kutzner, David van der Spoel, Martin Fechn...
ISJGP
2010
13 years 4 months ago
On the Hardware Implementation Cost of Crypto-Processors Architectures
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
Nicolas Sklavos
PC
1998
123views Management» more  PC 1998»
13 years 7 months ago
Designing communication strategies for heterogeneous parallel systems
This paper investigates communication strategies for interconnecting heterogeneous parallel systems. As the speed of processors and parallel systems keep on increasing over the ye...
Ravi Prakash, Dhabaleswar K. Panda
ICCD
1993
IEEE
90views Hardware» more  ICCD 1993»
13 years 11 months ago
Subterranean: A 600 Mbit/Sec Cryptographic VLSI Chip
In this paper the design of a high-speed cryptographic coprocessor is presented. This coprocessor is named Subterranean and can be used for both cryptographic pseudorandom sequenc...
Luc J. M. Claesen, Joan Daemen, Mark Genoe, G. Pee...