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» Continuous Parallel Coordinates
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ICIP
2009
IEEE
16 years 3 months ago
A High Throughput Cabac Algorithm Using Syntax Element Partitioning
Enabling parallel processing is becoming increasingly necessary for video decoding as performance requirements continue to rise due to growing resolution and frame rate demands. I...
125
Voted
HPCA
2003
IEEE
16 years 2 months ago
Dynamic Data Dependence Tracking and its Application to Branch Prediction
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
Lei Chen, Steve Dropsho, David H. Albonesi
173
Voted
HPCA
2003
IEEE
16 years 2 months ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston
136
Voted
ICCD
2006
IEEE
117views Hardware» more  ICCD 2006»
15 years 11 months ago
System-Level Energy Modeling for Heterogeneous Reconfigurable Chip Multiprocessors
—Field-Programmable Gate Array (FPGA) technology is characterized by continuous improvements that provide new opportunities in system design. Multiprocessors-ona-Programmable-Chi...
Xiaofang Wang, Sotirios G. Ziavras
109
Voted
IPPS
2009
IEEE
15 years 9 months ago
Crash fault detection in celerating environments
Failure detectors are a service that provides (approximate) information about process crashes in a distributed system. The well-known “eventually perfect” failure detector, 3P...
Srikanth Sastry, Scott M. Pike, Jennifer L. Welch