58 search results - page 6 / 12 » Controlled-Load Limited Switch Dynamic Logic Circuit |
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper addresses the problem of efficiently and accurately generating two-vector tests for crosstalk induced effects, such as pulses, signal speedup and slowdown, in digital c...
ICCAD
1998
IEEE
13 years 11 months ago
1998
IEEE
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
CDES
2006
13 years 9 months ago
2006
Abstract-- Digital signal processing (DSP) is used to perform filtering, decimation and down conversion in common communications systems, like in oversampling analog to digital con...
CDES
2008
13 years 9 months ago
2008
- The Cell Matrix Architecture is a massive array of dynamically self-configurable, uniformly connected, identical computational units. This architecture can enable efficient, prac...
VTS
2002
IEEE
14 years 13 days ago
2002
IEEE
Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test v...