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ICS
2005
Tsinghua U.
14 years 1 months ago
Improved automatic testcase synthesis for performance model validation
Performance simulation tools must be validated during the design process as functional models and early hardware are developed, so that designers can be sure of the performance of...
Robert H. Bell Jr., Lizy Kurian John
ISCAS
2007
IEEE
96views Hardware» more  ISCAS 2007»
14 years 1 months ago
Modeling and Synthesis of Hardware-Software Morphing
— In state of the art hardware-software-co-design flows for FPGA based systems, the hardware-software partitioning problem is solved offline, thus, omitting the great flexibil...
Dirk Koch, Christian Haubelt, Thilo Streichert, J&...
DAC
2001
ACM
14 years 8 months ago
Latency-Driven Design of Multi-Purpose Systems-On-Chip
Milenko Drinic UCLA Computer Science Dep. 4732 Boelter Hall Los Angeles, CA 90095-1596 milenko@cs.ucla.edu Darko Kirovski Microsoft Research One Microsoft Way Redmond, WA 98052 da...
Seapahn Meguerdichian, Milenko Drinic, Darko Kirov...
ESIAT
2009
IEEE
13 years 5 months ago
Path Planning Based on Dynamic Sub-population Pseudo-Parallel Genetic Algorithm
Through analysis of present pseudo-parallel genetic algorithm, propose a new dynamic sub-population pseudo-parallel genetic algorithm. It changes the condition that the magnitude o...
Lei Li, Yuemei Ren, Changyu Yang
VLSID
2006
IEEE
192views VLSI» more  VLSID 2006»
14 years 1 months ago
Beyond RTL: Advanced Digital System Design
This tutorial focuses on advanced techniques to cope with the complexity of designing modern digital chips which are complete systems often containing multiple processors, complex...
Shiv Tasker, Rishiyur S. Nikhil