141 search results - page 10 / 29 » Core Algorithms of the Maui Scheduler |
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
ISCA
2008
IEEE
14 years 2 months ago
2008
IEEE
Within-die process variation causes individual cores in a Chip Multiprocessor (CMP) to differ substantially in both static power consumed and maximum frequency supported. In this ...
DATE
2007
IEEE
14 years 2 months ago
2007
IEEE
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
ASPDAC
2005
ACM
13 years 10 months ago
2005
ACM
- To date, most high-level synthesis systems do not automatically solve present design problems, such as those related to timing associated with the physical implementation of mult...
ISPDC
2007
IEEE
14 years 2 months ago
2007
IEEE
Scheduling divisible loads in distributed systems is the subject of Divisible Load Theory (DLT). In this paper we show that coalitional game theory is a natural fit for modeling ...