275 search results - page 17 / 55 » Core architecture optimization for heterogeneous chip multip... |
ICCAD
2008
IEEE
14 years 5 months ago
2008
IEEE
— As transistor sizes continue to shrink and the number of transistors per chip keeps increasing, chip multiprocessors (CMPs) are becoming a promising alternative to remain on th...
ISCA
2011
IEEE
13 years 11 days ago
2011
IEEE
Network-on-chip (NoC) has become a critical shared resource in the emerging Chip Multiprocessor (CMP) era. Most prior NoC designs have used the same type of router across the enti...
DDECS
2008
IEEE
14 years 3 months ago
2008
IEEE
Abstract—In Network-on-Chip (NoC) application design, coreto-node mapping is an important but intractable optimization problem. In the paper, we use simulated annealing to tackle...
EUROPAR
2010
Springer
13 years 9 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
HPCA
2009
IEEE
14 years 9 months ago
2009
IEEE
Cache hierarchies in future many-core processors are expected to grow in size and contribute a large fraction of overall processor power and performance. In this paper, we postula...