Sciweavers

434 search results - page 47 / 87
» Core monitors: monitoring performance in multicore processor...
Sort
View
IPPS
2006
IEEE
14 years 3 months ago
A study of the on-chip interconnection network for the IBM Cyclops64 multi-core architecture
The designs of high-performance processor architectures are moving toward the integration of a large number of multiple processing cores on a single chip. The IBM Cyclops-64 (C64)...
Yingping Zhang, Taikyeong Jeong, Fei Chen, Haiping...
LCN
2005
IEEE
14 years 2 months ago
AntiWorm NPU-based Parallel Bloom Filters for TCP/IP Content Processing in Giga-Ethernet LAN
—TCP/IP protocol suite carries most application data in Internet. TCP flow retrieval has more security meanings than the IP packet payload. Hence, monitoring the TCP flow has mor...
Zhen Chen, Chuang Lin, Jia Ni, Dong-Hua Ruan, Bo Z...
GI
2004
Springer
14 years 2 months ago
CARUSO - Project Goals and Principal Approach
: This paper proposes CARUSO – a new SoC approach that emphasizes Connectivity, Autonomic/Organic computing principles, Real-time, and Ultra-low power requirements. The requireme...
Uwe Brinkschulte, Jürgen Becker, Klaus Dorfm&...
MICRO
2010
IEEE
173views Hardware» more  MICRO 2010»
13 years 6 months ago
Single-Chip Heterogeneous Computing: Does the Future Include Custom Logic, FPGAs, and GPGPUs?
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...
Eric S. Chung, Peter A. Milder, James C. Hoe, Ken ...
ISSAC
2009
Springer
155views Mathematics» more  ISSAC 2009»
14 years 3 months ago
Parallel sparse polynomial multiplication using heaps
We present a high performance algorithm for multiplying sparse distributed polynomials using a multicore processor. Each core uses a heap of pointers to multiply parts of the poly...
Michael B. Monagan, Roman Pearce