548 search results - page 30 / 110 » Core-Selectability in Chip Multiprocessors |
127
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ICCD
2002
IEEE
16 years 22 days ago
2002
IEEE
We present a co-simulation environment for multiprocessor architectures, that is based on SystemC and allows a transparent integration of instruction set simulators (ISSs) within ...
146
Voted
SEUS
2009
IEEE
15 years 10 months ago
2009
IEEE
Future embedded systems are expected to use chip-multiprocessors to provide the execution power for increasingly demanding applications. Multiprocessors increase the pressure on th...
136
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DATE
2008
IEEE
15 years 10 months ago
2008
IEEE
Efficient use of the memory hierarchy is critical for achieving high performance in a multiprocessor systemon-chip. An external memory that is shared between processors is a bottl...
144
Voted
ASAP
2005
IEEE
15 years 9 months ago
2005
IEEE
We studied the dynamic instruction count reduction for a single-thread, vectorized and a multi-threaded, non-vectorized, MPEG-4 video encoder. Results indicate a maximum improveme...
148
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IPPS
2007
IEEE
15 years 10 months ago
2007
IEEE
Snoopy cache coherence protocols broadcast requests to all nodes, reducing the latency of cache to cache transfer misses at the expense of increasing interconnect power. We propos...