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» Core-Selectability in Chip Multiprocessors
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CASES
2006
ACM
15 years 10 months ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
CCECE
2006
IEEE
15 years 10 months ago
QOS Driven Network-on-Chip Design for Real Time Systems
Real Time embedded system designers are facing extreme challenges in underlying architectural design selection. It involves the selection of a programmable, concurrent, heterogene...
Ankur Agarwal, Mehmet Mustafa, Abhijit S. Pandya
CAL
2008
15 years 4 months ago
BENoC: A Bus-Enhanced Network on-Chip for a Power Efficient CMP
Network-on-Chips (NoCs) outperform buses in terms of scalability, parallelism and system modularity and therefore are considered as the main interconnect infrastructure in future c...
I. Walter, Israel Cidon, Avinoam Kolodny
ICCD
2006
IEEE
128views Hardware» more  ICCD 2006»
16 years 28 days ago
Polaris: A System-Level Roadmap for On-Chip Interconnection Networks
Technology trends are driving parallel on-chip architectures in the form of multi-processor systems-on-a-chip (MPSoCs) and chip multi-processors (CMPs). In these systems the incre...
Vassos Soteriou, Noel Eisley, Hangsheng Wang, Bin ...
HOTI
2008
IEEE
15 years 10 months ago
A Network Fabric for Scalable Multiprocessor Systems
Much of high performance technical computing has moved from shared memory architectures to message based cluster systems. The development and wide adoption of the MPI parallel pro...
Nitin Godiwala, Jud Leonard, Matthew Reilly