Sciweavers

548 search results - page 60 / 110
» Core-Selectability in Chip Multiprocessors
Sort
View
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
15 years 8 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
ICS
2010
Tsinghua U.
15 years 2 months ago
An approach to resource-aware co-scheduling for CMPs
We develop real-time scheduling techniques for improving performance and energy for multiprogrammed workloads that scale nonuniformly with increasing thread counts. Multithreaded ...
Major Bhadauria, Sally A. McKee
ISQED
2010
IEEE
133views Hardware» more  ISQED 2010»
15 years 2 months ago
UC-PHOTON: A novel hybrid photonic network-on-chip for multiple use-case applications
Multiple use-case chip multiprocessor (CMP) applications require adaptive on-chip communication fabrics to cope with changing use-case performance needs. Networks-on-chip (NoC) ha...
Shirish Bahirat, Sudeep Pasricha
TCAD
2008
110views more  TCAD 2008»
15 years 2 months ago
A Reactive and Cycle-True IP Emulator for MPSoC Exploration
The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC inte...
Shankar Mahadevan, Federico Angiolini, Jens Spars&...
ASPDAC
2010
ACM
150views Hardware» more  ASPDAC 2010»
15 years 2 months ago
Post-silicon debugging for multi-core designs
Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are ...
Valeria Bertacco