237 search results - page 45 / 48 » Cost-Efficient Memory Architecture Design of NAND Flash Memo... |
CODES
2006
IEEE
14 years 29 days ago
2006
IEEE
Predicting timing behavior is key to efficient embedded real-time system design and verification. Especially memory accesses and co-processor calls over shared communication net...
SAMOS
2004
Springer
14 years 8 days ago
2004
Springer
— Architectural resources and program recurrences are the main limitations to the amount of Instruction-Level Parallelism (ILP) exploitable from loops, the most time-consuming pa...
DAC
2009
ACM
14 years 8 months ago
2009
ACM
State-of-the-art integral-equation-based solvers rely on techniques that can perform a matrix-vector multiplication in O(N) complexity. In this work, a fast inverse of linear comp...
GLVLSI
2005
IEEE
14 years 16 days ago
2005
IEEE
The instruction cache is a popular target for optimizations of microprocessor-based systems because of the cache’s high impact on system performance and power, and because of th...
ANSOFT
2002
13 years 6 months ago
2002
Abstract. The real-time process algebra (RTPA) is a set of new mathematical notations for formally describing system architectures, and static and dynamic behaviors. It is recogniz...