Modern processors rely on memory dependence prediction to execute load instructions as early as possible, speculating that they are not dependent on an earlier, unissued store. To...
Franziska Roesner, Doug Burger, Stephen W. Keckler
Value prediction is a relatively new technique to increase the Instruction Level Parallelism (ILP) in future microprocessors. An important problem when designing a value predictor...
Bart Goeman, Hans Vandierendonck, Koenraad De Boss...
For wireless channels, interference mitigation techniques are typically applied at the bit/packet transmission level. In this short paper, we present a simple channel predictor th...
To continue to improve processor performance, microarchitects seek to increase the effective instruction level parallelism (ILP) that can be exploited in applications. A fundament...
Abstract. This paper investigates the efficiency of in-door next location prediction by comparing several prediction methods. The scenario concerns people in an office building vis...
Jan Petzold, Andreas Pietzowski, Faruk Bagci, Wolf...