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ETS
2007
IEEE
94views Hardware» more  ETS 2007»
14 years 1 months ago
An Integrated Built-In Test and Repair Approach for Memories with 2D Redundancy
An efficient on-chip infrastructure for memory test and repair is crucial to enhance yield and availability of SoCs. Therefore embedded memories are commonly equipped with spare r...
Philipp Öhler, Sybille Hellebrand, Hans-Joach...
SEUS
2007
IEEE
14 years 1 months ago
A Framework for Hardware-in-the-Loop Testing of an Integrated Architecture
In this paper we present a distributed Hardware-in-the-Loop (HiL) simulation approach that supports the verification and validation activities in an integrated architecture as rec...
Martin Schlager, Roman Obermaisser, Wilfried Elmen...
ICCD
2004
IEEE
172views Hardware» more  ICCD 2004»
14 years 4 months ago
A Signal Integrity Test Bed for PCB Buses
Research in high-speed interconnect requires physical test to validate circuit models and design assumptions. At multi-Gbit/sec rates, physical implementations require custom circ...
Jihong Ren, Mark R. Greenstreet
VLSID
2009
IEEE
150views VLSI» more  VLSID 2009»
14 years 8 months ago
TIGUAN: Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability ANalysis
We present the automatic test pattern generator TIGUAN based on a thread-parallel SAT solver. Due to a tight integration of the SAT engine into the ATPG algorithm and a carefully ...
Alejandro Czutro, Ilia Polian, Matthew D. T. Lewis...
ATS
1998
IEEE
112views Hardware» more  ATS 1998»
13 years 11 months ago
Integrated Current Sensing Device for Micro IDDQ Test
A current sensing device, namely Hall Effect MOSFET (HEMOS) is proposed. It is experimentally shown that the HEMOS enables a non-contacting, and non-disturbing current measurement...
Koichi Nose, Takayasu Sakurai