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DATE
2007
IEEE
100views Hardware» more  DATE 2007»
14 years 1 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
ET
2002
90views more  ET 2002»
13 years 7 months ago
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
ITC
2003
IEEE
108views Hardware» more  ITC 2003»
14 years 25 days ago
Backplane Test Bus Applications For IEEE STD 1149.1
Prior to the mid 1980s, the dominance of through-hole packaging of integrated circuits (ICs) provided easy access to nearly every pin of every chip on a printed circuit board. Pro...
Clayton Gibbs
OOPSLA
2007
Springer
14 years 1 months ago
CUTE: C++ unit testing easier
This article describes the design and use of the CUTE C++ testing framework and its integration into the Eclipse C++ Development Tooling. Unit testing supports code quality and is...
Peter Sommerlad, Emanuel Graf
GLVLSI
2003
IEEE
180views VLSI» more  GLVLSI 2003»
14 years 25 days ago
3D direct vertical interconnect microprocessors test vehicle
The current trends in high performance integrated circuits are towards faster and more powerful circuits in the giga-hertz range and even further. As the more complex Integrated C...
John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan...