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GLVLSI
2007
IEEE
151views VLSI» more  GLVLSI 2007»
14 years 23 days ago
Hand-in-hand verification of high-level synthesis
This paper describes a formal verification methodology of highnthesis (HLS) process. The abstraction level of the input to HLS is so high compared to that of the output that the v...
Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Ma...
ICCTA
2007
IEEE
14 years 23 days ago
Register Sharing Verification During Data-Path Synthesis
The variables of the high-level specifications and the automatically generated temporary variables are mapped on to the data-path registers during data-path synthesis phase of hig...
Chandan Karfa, Chittaranjan A. Mandal, Dipankar Sa...
GLVLSI
2009
IEEE
113views VLSI» more  GLVLSI 2009»
14 years 23 days ago
Reducing parity generation latency through input value aware circuits
1 Soft errors caused by cosmic particles and radiation emitted by the packaging are an important problem in contemporary microprocessors. Parity bits are used to detect single bit ...
Yusuf Osmanlioglu, Y. Onur Koçberber, Oguz ...
3DPVT
2004
IEEE
141views Visualization» more  3DPVT 2004»
14 years 19 days ago
Exploitation of 3D Images for Face Authentication Under Pose and Illumination Variations
An appearance-based face authentication system integrating 2D color or intensity images and 3D data is presented in this paper. The proposed system is based on a low-cost 3D and c...
Filareti Tsalakanidou, Sotiris Malassiotis, Michae...
ADS
2004
Springer
14 years 19 days ago
Neural Architecture for Temporal Emotion Classification
Abstract. In this pilot study, a neural architecture for temporal emotion recognition from image sequences is proposed. The investigation aims at the development of key principles ...
Roland Schweiger, Pierre Bayerl, Heiko Neumann