The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...
Cherif Salama, Gregory Malecha, Walid Taha, Jim Gr...
In this paper, we propose a novel statistical capacitance extraction method for interconnects considering process variations. The new method, called statCap, is based on the spect...
PDE surfaces, whose behavior is governed by Partial Differential Equations (PDEs), have demonstrated many modeling advantages in surface blending, free-form surface modeling, and ...
We have devised a novel technique to automatically generate test cases for a software system, combining black-box model-based testing with white-box parameterized unit testing. Th...
Nicolas Kicillof, Wolfgang Grieskamp, Nikolai Till...
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...