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» Course on System Design (structural approach)
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PEPM
2009
ACM
15 years 10 months ago
Static Consistency Checking for Verilog Wire Interconnects
The Verilog hardware description language has padding semantics that allow designers to write descriptions where wires of different bit widths can be interconnected. However, many ...
Cherif Salama, Gregory Malecha, Walid Taha, Jim Gr...
GLVLSI
2008
IEEE
129views VLSI» more  GLVLSI 2008»
14 years 4 months ago
Variational capacitance modeling using orthogonal polynomial method
In this paper, we propose a novel statistical capacitance extraction method for interconnects considering process variations. The new method, called statCap, is based on the spect...
Jian Cui, Gengsheng Chen, Ruijing Shen, Sheldon X....
PG
2000
IEEE
14 years 2 months ago
Dynamic PDE Surfaces with Flexible and General Geometric Constraints
PDE surfaces, whose behavior is governed by Partial Differential Equations (PDEs), have demonstrated many modeling advantages in surface blending, free-form surface modeling, and ...
Haixia Du, Hong Qin
AMOST
2007
ACM
14 years 1 months ago
Achieving both model and code coverage with automated gray-box testing
We have devised a novel technique to automatically generate test cases for a software system, combining black-box model-based testing with white-box parameterized unit testing. Th...
Nicolas Kicillof, Wolfgang Grieskamp, Nikolai Till...
ISCA
2010
IEEE
199views Hardware» more  ISCA 2010»
14 years 1 months ago
Use ECP, not ECC, for hard failures in resistive memories
As leakage and other charge storage limitations begin to impair the scalability of DRAM, non-volatile resistive memories are being developed as a potential replacement. Unfortunat...
Stuart E. Schechter, Gabriel H. Loh, Karin Straus,...