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ICDE
2006
IEEE
206views Database» more  ICDE 2006»
14 years 9 months ago
Query Co-Processing on Commodity Hardware
The rapid increase in the data volumes for the past few decades has intensified the need for high processing power for database and data mining applications. Researchers have acti...
Anastassia Ailamaki, Naga K. Govindaraju, Dinesh M...
MICRO
2009
IEEE
132views Hardware» more  MICRO 2009»
14 years 2 months ago
EazyHTM: eager-lazy hardware transactional memory
Transactional Memory aims to provide a programming model that makes parallel programming easier. Hardware implementations of transactional memory (HTM) suffer from fewer overhead...
Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulka...
CODES
2007
IEEE
14 years 1 months ago
A code-generator generator for multi-output instructions
We address the problem of instruction selection for Multi-Output Instructions (MOIs), producing more than one result. Such inherently parallel hardware instructions are very commo...
Hanno Scharwächter, Jonghee M. Youn, Rainer L...
AGILEDC
2003
IEEE
14 years 25 days ago
YP and Urban Simulation: Applying an Agile Programming Methodology in a Politically Tempestuous Domain
YP is an agile programming methodology that has evolved over the past 15 years. Many of its features are common to other agile methodologies; its novel features include using a hi...
Bjørn N. Freeman-Benson, Alan Borning
ISCA
1996
IEEE
99views Hardware» more  ISCA 1996»
13 years 11 months ago
High-Bandwidth Address Translation for Multiple-Issue Processors
In an effort to push the envelope of system performance, microprocessor designs are continually exploiting higher levels of instruction-level parallelism, resulting in increasing ...
Todd M. Austin, Gurindar S. Sohi