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» Crosstalk Reduction by Transistor Sizing
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ICCAD
2008
IEEE
106views Hardware» more  ICCAD 2008»
14 years 4 months ago
Process variability-aware transient fault modeling and analysis
– Due to reduction in device feature size and supply voltage, the sensitivity of digital systems to transient faults is increasing dramatically. As technology scales further, the...
Natasa Miskov-Zivanov, Kai-Chiang Wu, Diana Marcul...
ISQED
2008
IEEE
186views Hardware» more  ISQED 2008»
14 years 1 months ago
Reliability-Aware Optimization for DVS-Enabled Real-Time Embedded Systems
—Power and energy consumption has emerged as the premier and most constraining aspect in modern computational systems. Dynamic Voltage Scheduling (DVS) has been provably one of t...
Foad Dabiri, Navid Amini, Mahsan Rofouei, Majid Sa...
JCP
2008
105views more  JCP 2008»
13 years 7 months ago
Thermal Driven Placement for Island-style MTCMOS FPGAs
Rapid increase in transistor density and operating frequency has led to the increase in power densities, exhibiting itself as a high temperature profile. The high temperature spots...
Javid Jaffari, Mohab Anis
TVLSI
2008
78views more  TVLSI 2008»
13 years 7 months ago
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime
Abstract--A SMART repeater is proposed for driving capacitively-coupled, global-length on-chip interconnects that alters its drive strength dynamically to match the relative bit pa...
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng...
ETS
2006
IEEE
118views Hardware» more  ETS 2006»
14 years 1 months ago
Living with Failure: Lessons from Nature?
- The resources available on a chip continue to grow, following Moore's Law. However, the major process by which the benefits of Moore's Law accrue, which is the continui...
Steve Furber