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» Crosstalk Reduction in Area Routing
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DAC
2002
ACM
14 years 10 months ago
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique
Reducing power dissipation is one of the most principle subjects in VLSI design today. Scaling causes subthreshold leakage currents to become a large component of total power diss...
Mohab Anis, Mohamed Mahmoud, Mohamed I. Elmasry, S...
VLSID
2005
IEEE
105views VLSI» more  VLSID 2005»
14 years 3 months ago
Placement and Routing for 3D-FPGAs Using Reinforcement Learning and Support Vector Machines
The primary advantage of using 3D-FPGA over 2D-FPGA is that the vertical stacking of active layers reduce the Manhattan distance between the components in 3D-FPGA than when placed...
R. Manimegalai, E. Siva Soumya, V. Muralidharan, B...
ISCAS
2005
IEEE
159views Hardware» more  ISCAS 2005»
14 years 3 months ago
A low power FPGA routing architecture
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...
Somsubhra Mondal, Seda Ogrenci Memik
FPGA
2001
ACM
128views FPGA» more  FPGA 2001»
14 years 2 months ago
Using sparse crossbars within LUT
In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like a full crossbar. Such a high degree of connectivity makes routing easier, bu...
Guy G. Lemieux, David M. Lewis
DAC
2006
ACM
14 years 10 months ago
A new hybrid FPGA with nanoscale clusters and CMOS routing
In this paper we propose a hybrid FPGA using nanoscale clusters with an architecture similar to clusters of traditional CMOS FPGAs. The proposed cluster is made of a crossbar of n...
Reza M. Rad, Mohammad Tehranipoor