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» Cycle count accurate memory modeling in system level design
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DATE
2008
IEEE
168views Hardware» more  DATE 2008»
14 years 1 months ago
Cycle-approximate Retargetable Performance Estimation at the Transaction Level
This paper presents a novel cycle-approximate performance estimation technique for automatically generated transaction level models (TLMs) for heterogeneous multicore designs. The...
Yonghyun Hwang, Samar Abdi, Daniel Gajski
CGO
2007
IEEE
14 years 1 months ago
Ubiquitous Memory Introspection
Modern memory systems play a critical role in the performance of applications, but a detailed understanding of the application behavior in the memory system is not trivial to atta...
Qin Zhao, Rodric M. Rabbah, Saman P. Amarasinghe, ...
TVLSI
2010
13 years 2 months ago
Variation-Aware System-Level Power Analysis
Abstract-- The operational characteristics of integrated circuits based on nanoscale semiconductor technology are expected to be increasingly affected by variations in the manufact...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
DAC
2004
ACM
14 years 8 months ago
High level cache simulation for heterogeneous multiprocessors
As multiprocessor systems-on-chip become a reality, performance modeling becomes a challenge. To quickly evaluate many architectures, some type of high-level simulation is require...
Joshua J. Pieper, Alain Mellan, JoAnn M. Paul, Don...
ICC
2007
IEEE
14 years 1 months ago
On the Impact of Ignoring Markovian Channel Memory on the Analysis of Wireless Systems
– Recent wireless measurement studies have revealed the presence of high-order memory in wireless bit-error channels. However, most wireless studies continue to employ the memory...
Syed A. Khayam, Hayder Radha