4 search results - page 1 / 1 » Cycle-Based Symbolic Simulation of Gate-Level Synchronous Ci... |
DAC
1999
ACM
13 years 11 months ago
1999
ACM
ICCAD
1991
IEEE
13 years 11 months ago
1991
IEEE
The program TRANALYZE generates a gate-level representation of an MOS transistor circuit. The resulting model contains only four-valued unit and zero delay logic primitives, suita...
CAV
1990
Springer
13 years 11 months ago
1990
Springer
Ternary system modeling involves extending the traditional set of binary values
KES
2005
Springer
14 years 27 days ago
2005
Springer
This paper presents a system for recognizing sketched logic circuits in real-time and graphically simulating them afterwords. It has been developed for use in university and school...