39 search results - page 5 / 8 » DELTEST: Deterministic Test Generation for Gate-Delay Faults |
DATE
2002
IEEE
14 years 2 months ago
2002
IEEE
Deterministic observation and random excitation of fault sites during the ATPG process dramatically reduces the overall defective part level. However, multiple observations of eac...
DSD
2005
IEEE
13 years 11 months ago
2005
IEEE
Several methods improving the fault coverage in mixed-mode BIST are presented in this paper. The test is divided into two phases: the pseudo-random and deterministic. Maximum of f...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
Energy Consumption Ratio (ECR) test, a current-based test, has shown its ability to reduce the impact of process variations and detect hard-to-detect faults. The effectiveness of ...
ITC
2003
IEEE
14 years 3 months ago
2003
IEEE
: The paper presents a novel technique for generating effective vectors for delay defects. The test set achieves high path delay fault coverage to capture smalldistributed delay de...
VTS
2000
IEEE
14 years 2 months ago
2000
IEEE
We propose a novel BIST technique for non-scan sequential circuits which does not modify the circuit under test. It uses a learning algorithm to build a hardware test sequence gen...