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» DFM DFY practices during physical designs for timing, signal...
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ASPDAC
2007
ACM
116views Hardware» more  ASPDAC 2007»
13 years 11 months ago
DFM/DFY practices during physical designs for timing, signal integrity, and power
Shi-Hao Chen, Ke-Cheng Chu, Jiing-Yuan Lin, Cheng-...
ISPD
2009
ACM
112views Hardware» more  ISPD 2009»
14 years 2 months ago
Post-floorplanning power/ground ring synthesis for multiple-supply-voltage designs
The multiple-supply voltage (MSV) design style has been extensively applied to mitigate dynamic-power consumption. The MSV design paradigm, however, brings many crucial challenges...
Wan-Ping Lee, Diana Marculescu, Yao-Wen Chang
ICCAD
1998
IEEE
94views Hardware» more  ICCAD 1998»
13 years 11 months ago
Noise considerations in circuit optimization
Noise can cause digital circuits to switch incorrectly and thus produce spurious results. Noise can also have adverse power, timing and reliability e ects. Dynamic logic is partic...
Andrew R. Conn, Ruud A. Haring, Chandramouli Viswe...