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USENIX
2007
13 years 10 months ago
Evaluating Block-level Optimization Through the IO Path
This paper focuses on evaluation of the effectiveness of optimization at various layers of the IO path, such as the file system, the device driver scheduler, and the disk drive i...
Alma Riska, James Larkby-Lahet, Erik Riedel
HPCC
2009
Springer
14 years 10 days ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are difficult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 2 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
DLOG
2006
13 years 9 months ago
Tableau Caching for Description Logics with Inverse and Transitive Roles
Abstract. Modern description logic (DL) reasoners are known to be less efficient for DLs with inverse roles. The current loss of performance is largely due to the missing applicabi...
Yu Ding, Volker Haarslev
CTRSA
2006
Springer
146views Cryptology» more  CTRSA 2006»
13 years 11 months ago
Cache Attacks and Countermeasures: The Case of AES
We describe several software side-channel attacks based on inter-process leakage through the state of the CPU's memory cache. This leakage reveals memory access patterns, whic...
Dag Arne Osvik, Adi Shamir, Eran Tromer