103 search results - page 1 / 21 » DPA Leakage Models for CMOS Logic Circuits |
CHES
2005
Springer
14 years 4 months ago
2005
Springer
In this paper, we propose new models for directly evaluating DPA leakage from logic information in CMOS circuits. These models are based on the transition probability for each gate...
CTRSA
2005
Springer
14 years 4 months ago
2005
Springer
There are many articles and patents on the masking of logic gates. However, the existing publications assume that a masked logic gate switches its output no more than once per cloc...
DATE
2005
IEEE
14 years 4 months ago
2005
IEEE
In nanometer scaled CMOS devices significant increase in the subthreshold, the gate and the reverse biased junction band-toband-tunneling (BTBT) leakage, results in the large incr...
CHES
2006
Springer
14 years 2 months ago
2006
Springer
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...
GLVLSI
2007
IEEE
13 years 11 months ago
2007
IEEE
This paper reviews the modeling of subthreshold leakage current and proposes an improved model for general series-parallel CMOS networks. The presence of on-switches in off-networ...