103 search results - page 11 / 21 » DPA Leakage Models for CMOS Logic Circuits |
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
In this paper we present a power dissipation model considering the charging/discharging of capacitance at the gate output node as well as internal nodes, and capacitance feedthrou...
VLSID
2002
IEEE
14 years 8 months ago
2002
IEEE
This paper presents a novel approach for the synthesis of dynamic CMOS circuits using Domino and Nora styles. As these logic styles can implement only non-inverting logic, convent...
ISQED
2010
IEEE
13 years 12 months ago
2010
IEEE
A simulation-based feasibility study of an intra-chip wireless interconnect system is presented. The wireless interconnect system is modelled in a 250 nm standard complementary met...
ICCAD
2006
IEEE
14 years 4 months ago
2006
IEEE
In this work we propose a methodology to self-consistently solve leakage power with temperature to predict thermal runaway. We target 28nm FinFET based circuits as they are more p...
ISQED
2003
IEEE
14 years 24 days ago
2003
IEEE
- This paper investigates important problems involved in the design of a CML buffer as well as a chain of tapered CML buffers. A new design procedure to systematically design a cha...