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» DPA Leakage Models for CMOS Logic Circuits
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GLVLSI
2009
IEEE
167views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Dual-threshold pass-transistor logic design
This paper introduces pass-transistor logic design with dualthreshold voltages. A set of single-rail, fully restored, passtransistor gates are presented. Logic transistors are imp...
Lara D. Oliver, Krishnendu Chakrabarty, Hisham Z. ...
INTEGRATION
2007
107views more  INTEGRATION 2007»
13 years 7 months ago
Power and electromagnetic analysis: Improved model, consequences and comparisons
Since their publication in 1998 and 2001 respectively, Power and Electromagnetic Analysis (SPA, DPA, EMA) have been successfully used to retrieve secret information stored in cryp...
Eric Peeters, François-Xavier Standaert, Je...
GLVLSI
2003
IEEE
229views VLSI» more  GLVLSI 2003»
14 years 25 days ago
Design issues in low-voltage high-speed current-mode logic buffers
- A current-mode logic (CML) buffer is based on a simple differential circuit. This paper investigates important problems involved in the design of a CML buffer as well as a chain ...
Payam Heydari
ASPDAC
2007
ACM
136views Hardware» more  ASPDAC 2007»
13 years 11 months ago
Design tool solutions for mixed-signal/RF circuit design in CMOS nanometer technologies
The scaling of CMOS technology into the nanometer era enables the fabrication of highly integrated systems, which increasingly contain analog and/or RF parts. However, scaling into...
Georges G. E. Gielen
DAC
2009
ACM
14 years 8 months ago
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Embedded cryptosystems show increased vulnerabilities to implementation attacks such as power analysis. CMOS technology trends are causing increased process variations which impac...
Lang Lin, Wayne P. Burleson