242 search results - page 17 / 49 » DYNORA: A New Caching Technique |
MICRO
2009
IEEE
14 years 2 months ago
2009
IEEE
Efficient memory hierarchy design is critical due to the increasing gap between the speed of the processors and the memory. One of the sources of inefficiency in current caches is...
IPPS
2002
IEEE
14 years 18 days ago
2002
IEEE
Tiling has long been used to improve cache performance. Recursion has recently been used as a cache-oblivious method of improving cache performance. Both of these techniques are n...
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
– Many embedded system designs usually impose (hard) read-time constraints on tasks. Thus, computing a tight upper bound of the worst case execution time (WCET) of a software is ...
ICIAP
2009
ACM
14 years 8 months ago
2009
ACM
In this paper we present an overview of the historical evolution of connected component labeling algorithms, and in particular the ones applied on images stored in raster scan orde...
MDM
2001
Springer
14 years 3 days ago
2001
Springer
The challenges ensuing from the asymmetric communication capabilities of mobile environments have led to an increased interest in broadcast-based data dissemination. Among the conc...