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SDL
2003
147views Hardware» more  SDL 2003»
13 years 9 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
DATE
2008
IEEE
145views Hardware» more  DATE 2008»
14 years 2 months ago
Minimizing Virtual Channel Buffer for Routers in On-chip Communication Architectures
We present a novel methodology for design space exploration using a two-steps scheme to optimize the number of virtual channel buffers (buffers take the premier share of the route...
Mohammad Abdullah Al Faruque, Jörg Henkel
IWMMDBMS
1998
123views more  IWMMDBMS 1998»
13 years 9 months ago
An Adaptive Block Management Scheme Using On-Line Detection of Block Reference Patterns
Recent research has shown that near optimal performance can be achieved by adaptive block replacement policies that use user-level hints regarding the block reference pattern. How...
Jongmoo Choi, Sam H. Noh, Sang Lyul Min, Yookun Ch...
DAC
2010
ACM
13 years 11 months ago
Automated compact dynamical modeling: an enabling tool for analog designers
In this paper we summarize recent developments in compact dynamical modeling for both linear and nonlinear systems arising in analog applications. These techniques include methods...
Bradley N. Bond, Luca Daniel
CODES
2002
IEEE
14 years 19 days ago
Communication speed selection for embedded systems with networked voltage-scalable processors
High-speed serial network interfaces are gaining wide use in connecting multiple processors and peripherals in modern embedded systems, thanks to their size advantage and power ef...
Jinfeng Liu, Pai H. Chou, Nader Bagherzadeh