Sciweavers

344 search results - page 48 / 69
» Data Driven Design Optimization Methodology: A Dynamic Data ...
Sort
View
ISSS
1995
IEEE
161views Hardware» more  ISSS 1995»
13 years 11 months ago
Synthesis of pipelined DSP accelerators with dynamic scheduling
To construct complete systems on silicon, application speci c DSP accelerators are needed to speed up the execution of high throughput DSP algorithms. In this paper, a methodology...
Patrick Schaumont, Bart Vanthournout, Ivo Bolsens,...
ASPLOS
2012
ACM
12 years 3 months ago
A case for unlimited watchpoints
Numerous tools have been proposed to help developers fix software errors and inefficiencies. Widely-used techniques such as memory checking suffer from overheads that limit thei...
Joseph L. Greathouse, Hongyi Xin, Yixin Luo, Todd ...
VEE
2012
ACM
187views Virtualization» more  VEE 2012»
12 years 3 months ago
DDGacc: boosting dynamic DDG-based binary optimizations through specialized hardware support
Dynamic Binary Translators (DBT) and Dynamic Binary Optimization (DBO) by software are used widely for several reasons including performance, design simplification and virtualiza...
Demos Pavlou, Enric Gibert, Fernando Latorre, Anto...
CODES
2001
IEEE
13 years 11 months ago
Compiler-directed selection of dynamic memory layouts
Compiler technology is becoming a key component in the design of embedded systems, mostly due to increasing participation of software in the design process. Meeting system-level ob...
Mahmut T. Kandemir, Ismail Kadayif
FPGA
2007
ACM
150views FPGA» more  FPGA 2007»
14 years 1 months ago
FPGA-friendly code compression for horizontal microcoded custom IPs
Shrinking time-to-market and high demand for productivity has driven traditional hardware designers to use design methodologies that start from high-level languages. However, meet...
Bita Gorjiara, Daniel Gajski