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» Data Memory Subsystem Resilient to Process Variations
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PRDC
2006
IEEE
14 years 1 months ago
SEVA: A Soft-Error- and Variation-Aware Cache Architecture
As SRAM devices are scaled down, the number of variation-induced defective memory cells increases rapidly. Combination of ECC, particularly SECDED, with a redundancy technique can...
Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai
MICRO
2007
IEEE
144views Hardware» more  MICRO 2007»
14 years 1 months ago
Process Variation Tolerant 3T1D-Based Cache Architectures
Process variations will greatly impact the stability, leakage power consumption, and performance of future microprocessors. These variations are especially detrimental to 6T SRAM ...
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Bro...
CORR
2010
Springer
148views Education» more  CORR 2010»
13 years 7 months ago
Perturbation Resilience and Superiorization of Iterative Algorithms
Iterative algorithms aimed at solving some problems are discussed. For certain problems, such as finding a common point in the intersection of a finite number of convex sets, there...
Yair Censor, R. Davidi, Gabor T. Herman
VLSID
2005
IEEE
147views VLSI» more  VLSID 2005»
14 years 8 months ago
Memory-Centric Motion Estimator
In the streaming video processing domain, the only way to meet strict performance and quality requirements and yet to provide the area- and power-wise optimal platform is to apply...
Aleksandar Beric, Ramanathan Sethuraman, Jef L. va...
JRTIP
2008
118views more  JRTIP 2008»
13 years 7 months ago
Custom parallel caching schemes for hardware-accelerated image compression
Abstract In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Fi...
Su-Shin Ang, George A. Constantinides, Wayne Luk, ...