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ISCA
2008
IEEE
201views Hardware» more  ISCA 2008»
13 years 9 months ago
iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures
Network-on-Chip (NoC) architectures have been adopted by a growing number of multi-core designs as a flexible and scalable solution to the increasing wire delay constraints in the...
Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
MICRO
2009
IEEE
128views Hardware» more  MICRO 2009»
14 years 3 months ago
mSWAT: low-cost hardware fault detection and diagnosis for multicore systems
Continued technology scaling is resulting in systems with billions of devices. Unfortunately, these devices are prone to failures from various sources, resulting in even commodity...
Siva Kumar Sastry Hari, Man-Lap Li, Pradeep Ramach...
HPCA
2008
IEEE
14 years 9 months ago
Uncovering hidden loop level parallelism in sequential applications
As multicore systems become the dominant mainstream computing technology, one of the most difficult challenges the industry faces is the software. Applications with large amounts ...
Hongtao Zhong, Mojtaba Mehrara, Steven A. Lieberma...
VLSID
2005
IEEE
116views VLSI» more  VLSID 2005»
14 years 9 months ago
A Quasi-Delay-Insensitive Method to Overcome Transistor Variation
Synchronous design methods have intrinsic performance overheads due to their use of the global clock and timing assumptions. In future manufacturing processes not only may it beco...
C. Brej, Jim D. Garside
APCSAC
2007
IEEE
14 years 3 months ago
A Power-Aware Alternative for the Perceptron Branch Predictor
Abstract. The perceptron predictor is a highly accurate branch predictor. Unfortunately this high accuracy comes with high complexity. The high complexity is the result of the larg...
Kaveh Aasaraai, Amirali Baniasadi