Sciweavers

213 search results - page 38 / 43
» Data Speculative Multithreaded Architecture
Sort
View
ISCA
2010
IEEE
176views Hardware» more  ISCA 2010»
14 years 1 months ago
Forwardflow: a scalable core for power-constrained CMPs
Chip Multiprocessors (CMPs) are now commodity hardware, but commoditization of parallel software remains elusive. In the near term, the current trend of increased coreper-socket c...
Dan Gibson, David A. Wood
ISPASS
2007
IEEE
14 years 3 months ago
Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads
Address re-mapping techniques in so-called active memory systems have been shown to dramatically increase the performance of applications with poor cache and/or communication beha...
Dhiraj D. Kalamkar, Mainak Chaudhuri, Mark Heinric...
FCCM
2006
IEEE
100views VLSI» more  FCCM 2006»
14 years 3 months ago
Enabling a Uniform Programming Model Across the Software/Hardware Boundary
In this paper, we present hthreads, a unifying programming model for specifying application threads running within a hybrid CPU/FPGA system. Threads are specified from a single p...
Erik Anderson, Jason Agron, Wesley Peck, Jim Steve...
PPPJ
2006
ACM
14 years 3 months ago
Enabling Java mobile computing on the IBM Jikes research virtual machine
Today’s complex applications must face the distribution of data and code among different network nodes. Java is a wide-spread language that allows developers to build complex so...
Giacomo Cabri, Letizia Leonardi, Raffaele Quitadam...
IEEEPACT
2005
IEEE
14 years 2 months ago
Maximizing CMP Throughput with Mediocre Cores
In this paper we compare the performance of area equivalent small, medium, and large-scale multithreaded chip multiprocessors (CMTs) using throughput-oriented applications. We use...
John D. Davis, James Laudon, Kunle Olukotun